Detector arrays are used in a wide variety of imaging systems for industrial as well as scientific applications. For example, detector arrays have been recently widely used in nuclear medical imaging techniques, such as Positron Emission Tomography (PET). In such an application 511 keV gamma rays emitted from a human body strike pixelated scintillators which create light in response to the received radiation. Each illuminated pixel of the pixelated scintillator is detected by a respective photodiode of the detector array that converts the light into electrical signals used for imaging purposes. During data collection, each pixel provides an electrical output signal proportional to the absorbed photon flux. These output signals are then processed to create an image of the internal features of the subject (See M. Mazzillo et al., Silicon Photomultipliers for Nuclear Medical Imaging Applications, Proc of SPIE, Optical Sensors 2008, Vol. 7003 70030I-1).
Schottky photodiodes are majority carrier devices, and as such, they may be preferred because they allow a faster timing response than conventional p-n junctions. In Trench Sidewall Contact Schottky Photodiode and related method of fabrication, VA2009A000033, filed Jun. 1, 2009 to M. C. Mazzillo, a vertical Schottky photodiode structure is disclosed. The thickness of the depleted region of which is adjusted by varying the depth of metal contact trenches in a lightly doped semiconductor epilayer, and even the thickness of the epilayer may be reduced to trim the sensitivity of the device to high wavelength photons.
Of course, single pixels or photo detector arrays, including Schottky photodiodes, can be used for detecting the radiation without using any scintillator material, as, for example, in spectroscopic and astronomical imaging applications where the electromagnetic radiation to be detected is in the range of sensitivity of the semiconductor used for the photo sensor fabrication.
Charged Coupled Device (CCD) technology is commonly used for imaging applications due to its relatively high quantum efficiency in the visible band and low readout noise, even at relatively high scan rates. In recent years CMOS-Active Pixel Sensors (APS) have been developed and used for high speed imaging applications, for example, in adaptive optics, star trackers, and fast video-rate readout systems. Though CCD devices exhibit better performance in terms of high fill factor and, consequently, high quantum efficiency and low noise, CMOS APS devices may be more used because of their superior response performances, low fabrication cost, and easy foundry access (See G. Bonanno et al., CMOS-APS for Astrophysical Applications, Memorie Salt 2003, Vol. 74, pp. 800-803).
A great effort has been recently spent for the realization of SPAD (Single Photon Avalanche Diode) imaging arrays, which by exploiting the faster time response (<100 ps) of photodiodes allow a three-dimensional imaging of the objects by using time-of-flight techniques. The packaging of these devices and the integration of the detector with the ancillary electronics is a quite complex matter, and lately various techniques have been developed to realize compact and cheap “packaging” approaches.
In any case, large area and high fill factor arrays may be desired. The pixels of which should be individually addressable by independent driving and readout circuits. The larger the number of pixels in the array the greater the dynamic range, and thus the more accurate the spatial information provided by the whole photo detector. Indeed, the larger the size and the geometrical fill factor of the array, the greater its sensitivity.
According to semiconductor device fabrication processes, chips are built up in large numbers on a single large “wafer” of semiconductor material, typically silicon. The individual chips are patterned with small pads of metal (usually near their edges) for connections to leads of a metal frame. The chips are then cut out of the wafer bonded to a metal frame or carrier, and the pads are connected to the metal leads, typically with small wires (wire bonding). In case of a multi-pixel array, an individual connection of each array pixel to an external circuitry may be desired, and for arrays with a large number of pixels wire bonding may become practically impossible because of packaging constraints.
A possible approach to overcome this problem may be to integrate the sensor and the electronics in a compatible technology process flow such that by integrating complex multiplexed electronics architectures, the overall number of external leads may be made compatible with the packaging constraints of evidence. However, this approach significantly reduces the area occupancy ratio between sensing area and overall chip area (geometrical fill factor) limiting the dynamic range and/or sensitivity (See Niclass et al., Design and Characterization of a CMOS 3-D Image Sensor Based on Single Photon Avalanche Diodes, IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, pp. 1847-1854, 2005). Moreover, it may not be possible to integrate the electronics and the photo sensor fabrication technologies in a monolithic device fabrication process.
Integration of a detector array with ancillary electronics may be made possible by using more complex packaging techniques like “Flip Chip” or “Bridge” Bonding. Both contemplate bonding of two distinct chips face-to-face and illuminating the detector array from the substrate side (so-called back illumination). In Flip Chips the semiconductor detector cells are “bump-bonded” to readout circuits by defined arrays of indium (In) or solder bumps. Such a technique has been used, for example, for indium-gallium-arsenide (InGaAs) photodiodes grown epitaxially on indium-phosphide (InP) substrates. In this case, the substrate material is relatively transparent at the wavelength where the epitaxially thick detector is used so that the devices can be used in back-illuminated mode without eliminating the substrate onto which they were formed. However, in other situations, for example, in homo-epitaxial devices realized on silicon or on silicon carbide, the substrate is optically opaque at wavelengths the detector has to be used, and therefore, it may be desirable to remove the substrate leaving a detector structure that may be only a few microns thick. In such a “bump-bonding” process, a sufficient mechanical sturdiness may be ensured by filling the spaces between the bumps before detector substrate removal. Concerns about the scalability of this type of process to large array sizes led to the development of an alternative process known as “bridge bonding” (See B. F. Aull et al., Geiger-Mode Avalanche Photodiodes for Three-Dimensional Imaging, Lincoln Laboratory Journal, Vol. 13, No. 2, pp. 335-350, 2002).
In a “bridge bonding” process, the detector array and the electronics chips are epoxied together, and detector substrate removal is carried out. Electrical connections are made last by etching vias between the photodiodes and patterning metal connections in the vias. Successful development of the bridge-bonding process required overcoming a number of technological hurdles. First of all, the thinning must be uniform. Then curing of the epoxies used must not lead to destructive mechanical stresses due to thermal-expansion coefficient mismatch between semiconductors and epoxies. The vies through the epoxy must have sloped sidewalls to allow good step coverage of the bridge metal. Moreover because of the vias, most of the required photolithographic steps are done on a non-planar surface, which raises some problems of non-uniform photo resist thickness and exposure depth-of-focus issues. Finally, handling of the photo detector wafer should not lead to excessive increases in leakage current or dark count rate (See B. F. Aull et al., Geiger-Mode Avalanche Photodiodes for Three-Dimensional Imaging, Lincoln Laboratory Journal, Vol. 13, No. 2, pp. 335-350, 2002).
A possible way to front illuminate the detector for avoiding removal of the substrate is to use Through Silicon Vies (TSVs) for the integration of the detector with the electronics. TSV is a vertical electrical connection (via) passing completely through a silicon wafer or die, and at present, may potentially be the best technique of system integration. In this case, the detector die and the electronics chips are vertically stacked, and the contacts from the topside of the detector are realized through vias to the backside of the die, then suitably soldered to the driving and readout circuitry.
The through-via technology made remarkable advances in the latter half of the 90 s, when important process technologies, such as deep silicon etching, wafer thinning, and wafer/chip bonding were developed. However, high cost of these techniques make them unsuited for low-end products (See K. Takahashi and M. Sekiguchi, Through Silicon Via and 3-D Wafer/Chip Stacking Technology, 2006 Symposium on VLSI Circuits, pp. 89-92).